1. Field
Exemplary embodiments of the present invention relate to an integrated circuit system.
2. Description of the Related Art
In the field of an integrated circuit system, a packaging technology for a semiconductor device may include features such as miniaturization and high capacity. Various techniques for stacked semiconductor packages may provide satisfactory results in terms of mounting efficiency as well as miniaturization and high capacity.
A stacked semiconductor package may be manufactured through a method of stacking individual semiconductor chips and simultaneously packaging the stacked semiconductor chips and a method of stacking individually packaged semiconductor packages. Semiconductor chips of a stacked semiconductor package are electrically connected through metal wires or through-silicon vias (TSVs).
In a conventional stacked semiconductor package using metal wires, since electrical signals are exchanged through metal wires, an operation speed decreases. Also, since a number of metal wires are used, the electrical characteristics of the stacked semiconductor package may be degraded. Further, in the conventional stacked semiconductor package, because additional area for forming the metal wires is required, the overall size of the stacked semiconductor package increases, and because gaps are required for wire-bonding of semiconductor chips, the overall height of the stacked semiconductor package increases.
In general, a stacked semiconductor package using through-silicon vias includes via holes defined to pass through semiconductor chips, through-silicon vias formed by filling a conductive substance in the via holes, and an upper semiconductor chip and a lower semiconductor chip electrically connected by the TSVs.
A stacked semiconductor package generally includes at least one master chip and a plurality of slave chips. The master chip is a chip that controls the plurality of slave chips and interfaces with a circuit outside of the stacked semiconductor package, and the slave chips are chips that operate under the direct control of the master chip or under the control of the signal transmitted through the master chip. Hereafter, operations of the stacked semiconductor package will be described by exemplifying a memory system.
In a memory system, a master chip generally is a chip that is placed at a lowermost position in the stacked semiconductor package, is applied with a command, an address, data signals, and so forth from a memory controller, and transmits them to slave chips. The master chip may also serve as an interface for transmitting the output data of the slave chips to the memory controller. A plurality of slave chips store or output data using the command and address that are transmitted through the master chip. In this example, the operation speeds of the plurality of slave chips may become different from one another according to processing or PVT (process, voltage and temperature) conditions.
Here, how the operation speeds of the plurality of slave chips become different from one another will be described by exemplifying a read operation. When a read command and an address are applied from the memory controller, the master chip transmits the read command and the address to the respective slave chips. Each slave chip combines the read command and the address and generates a signal for outputting data and a signal for determining a time when outputted data is transmitted to the master chip. The signal for determining a time when outputted data is transmitted to the master chip is generally referred to as a strobe signal. The strobe signal is generated through logic that is not synchronized with a clock in the slave chip. In this regard, the delay value of the logic for generating the strobe signal changes depending upon processing by which the slave chip is manufactured or PVT conditions. Thus, in the respective slave chips, times when strobe signals are activated become different from one another, and as a result, times when the output data of the respective slave chips are loaded on the through-silicon vias and are transmitted to the master chip become different from one another. More specifically, a skew occurs in terms of tAA (data access time) in the specification defined in a DRAM.
The master chip transmits the data transmitted from the plurality of slave chips to the memory controller using the clock generated therein or applied thereto. Accordingly, if the times when the data of the respective slave chips are transmitted to the master chip become different from one another, a margin decreases due to the occurrence of the skew.